The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
作者:
Blaauw D.;Flautner K.;Sylvester D.;Bo Zhai
通讯作者:
Zhai, B
作者机构:
ARM Ltd, Cambridge CB1 9NJ, England.
Univ Michigan, Adv Comp Architecture Lab, Ann Arbor, MI 48109 USA.
通讯机构:
Univ Michigan, Adv Comp Architecture Lab, Ann Arbor, MI 48109 USA.
语种:
英文
期刊:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ISSN:
1063-8210
年:
2005
卷:
13
期:
11
页码:
1239-1252
摘要:
Dynamic voltage scaling (DVS) is a popular approach for energy reduction of integrated circuits. Current processors that use DVS typically have an operating voltage range from full to half of the maximum V/sub dd/. However, there is no fundamental reason why designs cannot operate over a much larger voltage range: from full V/sub dd/ to subthreshold voltages. This possibility raises the question of whether a larger voltage range improves the energy efficiency of DVS. First, from a theoretical point of view, we show that, for subthreshold supply voltages, leakage energy becomes dominant, making "just-in-time computation" energy-inefficient at extremely low voltag...